HMC704LP4E【PDF 26/44 页】IC FRACT-N PLL 16BIT 24QFN

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HMC704LP4E

v03.1211

8 GHz fractionaL-n PLL

For price, delivery, and to place orders: Hittite Microwave Corporation,20 Alpha Road, Chelmsford, MA 01824

Phone: 978-250-3343

Fax: 978-250-3373

Order On-line at www.hittite.com

Application Support: Phone: 978-250-3343 or apps@hittite.com

HMc Mode - Serial Port rEaD operation

A typical HMC Mode READ cycle is shown in Figure 37.

a. The Master (host) asserts both sEN (serial Port Enable) and sDI to indicate a READ cycle, followed

by a rising edge sCLK. Note: The Lock Detect (LD) function is usually multiplexed onto the LD_sDO

pin. It is suggested that LD only be considered valid when sEN is low. In fact LD will not toggle until

the first active data bit toggles on LD_sDO, and will be restored immediately after the trailing edge

of the LsB of serial data out as shown in Figure 37.

b. The slave (PLL) reads sDI on the 1st rising edge of sCLK after sEN. sDI high initiates the READ

cycle (RD)

c. Host places the six address bits on the next six falling edges of sCLK, MsB first.

d. slave registers the address bits on the next six rising edges of sCLK (2-7).

e. slave switches from Lock Detect and places the requested 24 data bits on sD_LDO on the next 24

rising edges of sCK (8-31), MsB first .

Host registers the data bits on the next 24 falling edges of sCK (8-31).

g. slave restores Lock Detect on the 32nd rising edge of sCK.

h. sEN is de-asserted on the 32nd falling edge of sCLK.

The 32nd falling edge of sCLK completes the READ cycle.

table 10. SPi HMc Mode - read timing characteristics

Parameter

Conditions

Min.

Typ.

Max.

Units

sEN to sCLK setup time

sDI setup to sCLK time

sCLK to sDI hold time

sEN low duration

sCLK to sDO delay

8.2ns+0.2ns/pF

Figure 37. HMC Mode Serial Port Timing Diagram - READ

sCLK

sDI

sEN

LD_sDO

d23

d22

LD (Lock Detect)

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